Speech compressor with gap filling

ABSTRACT

An improved speech compressor provides frequency transformation by passing speech signals through an analog shift register and controlling the shift rate of the register with a linearly varying periodicity with noise cancellation of the characteristic noise in the shift registers and the control of the sample period and output blanking to improve the signal output characteristic and minimize noise components therein. The system provides a single compression-expansion manual control which varies the record reproducer transport speed and the rate of change of the linearly varying pulse periodicity to provide a unitary control for selecting the corresponding compression ratio and automatically modifies the sample period to optimize the signal and discard intervals as the selected compression or expansion ratio is changed. Automatic initiation of reset in response to detection of a zero crossing of the audio output signal is provided and auxiliary fixed storage is used to fill blanking gaps in the output signal.

[75] Inventor: Murray M. Schiffman, Westport,

Conn.

[731 Assignees: Cambridge Research and Development Group, Westport, Conn.; Sanford D. Greenberg, Washington, DC; DT Liquidating Partnership, New York, N.Y.; Murray M. Shiffman, Westport, Conn.

[22] Filed: Jan. 14, 1974 [21] Appl. No.: 430,911

Related US. Application Data {63] Continuation'in-part of- Ser. No. 331,550, Feb. 12,

1973, Pat. No. 3,828,361, which is a continuationin-part of Ser. No. 171,571, Aug. 13, 1971, Pat. No. 3,786,195 [52] US. Cl. 360/8, 179/1555 T, 360/25 [51] Int. Cl....G11b.5/00, G1 lb 15/18, Gllb 19/28 [58] Field of Search.... 179/1 SA, 1555 T, 15.55 R; 178/66 TC; 360/8, 25, 26, 36

[56] References Cited UNITED STATES PATENTS 2,816,175 12/1957 Blaney 360/66 3,319,013 5/1967 Hodder 3.409.736 11/1968 Hurst et a1... 3.409743 1 H1968 Greefkes 360/8 United States Patent 1 [111 3,869,708

. Schiffman Mar. 4, 1975 [5 SPEECH COMPRESSOR wrrn GAP 3,621,150 1/1971 Pappas, 360/8.

FILLING 3,763,328 10/1973 Lester et a1 360/8 OTHER PUBLICATIONS Lee, Time Compression and Expansion of Speech by the Sampling Method, Nov. 1972, Journal of the Audio Eng. Society, Vol. 20, No. 9, pages 738-742.

Primary E.\'aminerAlfred H. Eddleman Attorney, Agent, or FirmCharles E. Pfund [57] ABSTRACT An improved speech compressor provides frequency transformation by passing speech signals through an analog shift register and controlling the shift rate of the register with a linearly varying periodicity with noise cancellation of the characteristic noise in the shift registers and the control of the sample period and output blanking to improve the signal output characteristic and minimize noise components therein. The system provides a single compression-expansion manual control which varies the record reproducer trans port speed and the rate of change of the linearly varying pulse periodicity to provide a unitary control for selecting the corresponding compression ratio and automatically modifies the sample period to optimize the signal and discard intervals as the selected compression or expansion ratio is changed. Automatic initiation of reset in response to detection of a zero crossing of the audio output signal is provided and auxiliary fixed storage is used to fill blanking gaps in the output signal.

6 Claims, 12 Drawing Figures VOLUME '2 H CONTROL 2| 22 23 stat 25 32 PRE AMP FREQUENCY MOTOR HEAD EQUALIZER PROCESSOR AME i z l l '5 CONTROL 24' CIRCUIT 26 1 l 17 I I 29 TONE CONTROL PATENTEDIIAR 1 75 3,869,708

I SHLU 1 [If 3 I VOLUME H CONTROL QI E E B PLAYBACK I PRE AMP FREQUENCY MP COMPRESSED MOTOR HEAD EQUALIZER PRocEssOR SPEACH cONTROL 24 CIRCUIT I 26 I i I I @iQMEBESfiQNlAUQ- L I 29 @COWREOL 72 AUDIO IN 256 68 STAGE 7| It 69 256 FIG. 2 I STAGE I|r ;2 3I I? I r I VOLTAGE AUDIO AMP I I 46 CONTROLLED I 66 ND ZERO- I AUDIO I MC RAMP vc PERIOD CROSSING I OUT f(c) GENERATOR GENERATOR T' S DETECTOR I I F|G.4A (VCP) I (GA|N=|) 25 I A 74 4 g I f FIG. 2 I RES PULSE II To KT I REsET I I RAMP;O 48\ I 835T /I/75 ,V or .8v 1 I79 I I 43g BLANK I EQQ 83 I ZERO- I ENABLE I RESET BLANK cRosslNe V I EC AND AuTo I I\ D FF PULSES RESET I FIG 4A I I 49 6- I I I 8| R rel I I 82 wi l; J Minn-" .l

I I III I21,,v T /6O F|G.2A r 0 I I :35 VGT- 62 F PATENTEBHAR 4I975 3,869,708

sIIIEI2I f3 ENABLE BLANK 49 I I AT 2.0.

I 256-| FIG. 3C I IIIIIIIIIIIIHI I I FORCES 78 BLANK 46 I F 94 I09 FIG. 4A I +2 95 I06 92 I +3 I 52 47 93 l I 96 BLANK EC \I ENABLE RESET Kv ll E LHWV 49 8&5;

- /l s l 97 I I r g 98 53 I I I No l I LIL ALWAYS RESET FIG.4B E 78 was VEC

RESET z.c. LEvEL ALWAYS RESET ALWAYS RESET FIG. 4C ER(EV \IoLTs z.c. RESET REGION EXPANSION I 'TmIn. I APPROXIMATELY CONSTANT PERIOD IN EXPANSION 1 SPEECH COMPRESSOR WITH GAP FILLING cRoss REFERENCE TO RELATED APPLICATIONS BACKGROUND OF THE INVENTION This invention relates generally to sound or speech compressors in which a sound recording is reproduced at a speed different than the speed at which the sound was recorded and the frequency components of the recorded signal are restored to approximate those of the normal speech which was recorded thus permitting a recording to be played back with normal speech frequencies but at an elapsed time different than that in which the recording was made. If the playback transport is run at a higher speed than the recording speed the time is compressed and the information is played back in less time than was taken to record it. If the transport is run at a slower speed than its recording speed the time is expanded and the information conveyed in a longer time than it took to record. In this application, compression will be used generically to mean both time compression and time expansion hence the compression ratio, C, is greater than one for time compression and a value between zero and less than one for time expansion.

SUMMARY OF THE INVENTION The present invention provides in a speech compressor-expander an improved ramp generator for controlling a voltage controlled period generator to generate a linearly-varying-periodicity square wave for controlling the shift period of analog shift registers through which the time-compressed sound signal passes for frequency restoration. The motor speed control and the ramp generator are controlled from a single manual control to select the compression ratio thereby coordinating the speed at which the transport motor runs with the selection of the ramp slope to ultimately control the rate of change of the linear period variation of the square wave generator thus providing the desired frequency transformation for restoring the normal frequency spectrum of the sound or speech signals. In passing the signal through the analog shift registers the delay registers are separated into two equal sections and the signal is shifted through the two halves of the analog shift register with a signal inversion imposed for the signals which pass through one-half of the register. The signals are combined from the outputs of the two halves of the register either arranged serially or in parallel and in either event the processing disturbance component introduced by applying the linearly varying square wave as the shift period for the registers is cancelled by the inversion technique whereas the sound signal components are additive thereby improving the signal level and greatly decreasing the processing noise component level. At the end of the periodic variation of the analog shift registers the present invention provides improved zero crossing detection for the signal and operates to blank the audio output during reset of the ramp and control period generators during discard of the signal stored therein and the period it takes to reload the register prior to output signal once again appearing at the output terminals thereof. In addition, the present invention provides an improved control of the repetitive sample period to optimize the relation of sample and discard time with the characteristics of human speech and the selected compression ratio. Signal storage for filling the time interval during reset (i.e., gap filling) is provided which is particularly useful during expansion where the gap in the output signal may otherwise be objectionable at low expansion ratios.

DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram partly pictorial of an overall speech compression system according to the invention.

FIG. 2 is an overall block diagram partly schematic of a signal processor and control circuits therefor in accordance with the invention.

FIG. 2A is a schematic diagram of the voltage controlled period generator. FIG. 2B is a waveform diagram useful for explaining the operation of FIG. 2A.

FIG. 3C is waveform diagram of the blank enable and blank gating control of the output.

FIG. 4A is a schematic diagram of the blank enable and automatic reset circuit.

FIG. 4B is a diagram of the ramp generation operation with varying period for compression.

FIG. 4C is a diagram of the ramp generation operation with approximately constant period for expansion.

FIG. 5 is a block diagram of additional circuitry to provide gap filling.

FIG. 6 shows a modification of FIG. 4A to provide an automatic variation in repetition period for expansion.

FIG. 6A shows the operating characteristic for the circuit of FIG. 6.

FIG. 6B is a diagram showing the ramp generation operation using the modification shown in FIG. 6 to provide a varying repetition period for time expansion.

DESCRIPTION OF THE PREFERRED EMBODIMENT Referring now to FIG. 1, a self-contained tape playback unit incorporating speech compression features in accordance with the invention is shown. The unit comprises the usual record storage and transport system for relatively moving a sound record past the transducer to obtain an electrical signal representative of the recorded sound. As shown in FIG. 1 a pair of reels 11 and 12 contain a magnetic tape recording 13 which is drawn past a playback head 14 when the reels 11 and 12 are rotated with or without a capstan drive for the tape as is known in the art and the transducer in playback head 14 produces on line 15 an electrical signal representing the sound recorded on the tape 13. The frequency spectrum of the electrical signal on line 15 will be determined by the speed at which the tape 13 is moved past the transducer in the playback head 14 and for this purpose the drive of the reels 11, 12 and/or the capstan on the tape 13 is controlled by a variable speed motor 16. The speed is selected by manual control 17 which can be set for a range of speeds which includes speeds equal to, greater than, and less than the speed at which the sound recording was initially impressed on the tape 13.

The signal on line passes through a preamplifier equalizer 21 which may have automatic volume control and otherwise is adapted to condition the signal and compensate for the frequency response involved in the magnetic recording and transducing system and produce a relatively constant amplitude audio analog signal on line 22 representing the sound signal. The signal on line 22 is passed through a frequency conversion processor 23 which operates under the control of a control circuit 24 to convert the frequency spectrum of the signals on line 22 into normal range speech frequency signals on line 25. The features of the circuits 23 and 24 are described in detail hereinafter.-

The frequency restored signal on line 25 is amplified for audio reproduction in an amplifier 26 which may have the usual volume control 27 and tone control 28 and is further subject to a blanking control 29 to produce an output signal on line 31 which is transduced into an audible reproduction by the audio transducer 32. In order to coordinate the operation of the device to provide frequency transformation corresponding to that required by the speed selected for the motor 16, the manual control 17 also is coupled as indicated at 33 to control the operation of control circuit 24 and frequency processor 23 to obtain the desired frequency restoration of the signals being processed through unit 23.

Referring now to FIG. 2 the general arrangement of the frequency processor 23 and control circuit 24 will be described.

Manual control 17 selects motor speed by means of control circuit 44. The motor control circuit 44 also provides an output signal in accordance with the setting of C which is applied to an f(c) circuit 45 which transforms the linear setting of C on control 17 to a voltage on line 41 which may, for example, provide the function C K c l/C +1 as the functional relation for establishing the ramp slope as a function of compression factor C.

As disclosed in applicants copending applications, delay which is a continuous function varying linearly with time at rate d throughout the sample period produces the desired frequency transformation where d 2 C l/C 1. For incremented delay such as obtained with analog shift registers controlled by shift pulses of geometrically progressing period this relation for the f(c) function with respect to the instantaneous incremental delay, d, provides an accurate frequency transformation particularly for moderate values of C. Where large values of compression are desired (for example,

C O.5 or C 2.0) a more accurate function for a,

which takes into account increasing quantization deviation, is:

This flc) input on line 41 to ramp generator 42 pro duces on output line 46 a ramp voltage which has a predetermined slope and repetition interval determined by the input voltage on line 41. The ramp generator 42 re sets from signal on line 53 and the slope of the ramp is determined by the input signal on line 41. The basic period of the ramp will decrease as the slope increasesfor compression ratios of C greater than one and may also provide this feature for values of C less than one as hereinafter described.

The V voltage on line 41 is applied on line 47 to a blank enable circuit 43 which determines whether the unit is in compression or expansion mode by sensing the voltage on line 47 relative to a fixed level such as 7.8 volts. When the voltageon line 47 is above 7.8 volts the unit iscompressing speech for C greater than one and for this condition the blank enable circuit 43 will v produce two outputs as the ramp excursion approaches its end value of 2.0 volts. By sensing an input on line 48, from the output of ramp generator 42 on line 46, the blank enable circuit 43 produces on line 49 a blank enable signal when the input on line 48 crosses the three volt level and produces a reset signal on line 51, when the signal on line 48 reaches the two volt level which is the designated end of the ramp period. If the end of the ramp period is reached by the ramp voltage reaching the two volt level, the reset pulse on line 51 will trigger a one shot 52 which is connected on line 53 to reset the ramp generator 42 and at the end of the reset one shot pulse which resets the ramp generator 42 to 7.8 volts the next ramp excursion begins. The length of the reset one shot pulse from unit 52 is long enough to permit the ramp generator to reset to 7.8 volts as a starting point.

The output V of the ramp generator 42 is applied to a voltage controlled period generator 54 which gener ates on line 55 a square wave output which has a pulse period that varies linearly with the linear variation of the ramp voltage V One form of the voltage controlled period generator 54 is shown in FIG. 2A to comprise a current generator 56 generating current I and a current generator 57 generating selectively a current 2I in the opposite direction both currents being used to charge and discharge a capacitor 58. The current I, through generator 56 flows continuously and the current 21 through generator 57 flows in the opposite direction slectively to establish the voltage across capacitor 58. Controlof the generator 57 is in accordance with the function V established as an on and off signal from the output 60 of a flip-flop 59. The state of the flip-flop 59 is established by the outputs of two voltage comparators 61 and 62 which each have as inputs the voltage V from capacitor 58. For comparator 61 the other input is a voltage E which is at a fixed predetermined level. For the other input of comparator 62 the input voltage V from the ramp generator42 is applied. The fixed voltage E is always greater than the input voltage V The operation of the circuit of FIG. 2A can be explained with reference to the diagram of FIG. 28 where the constant voltage E is indicated and the discharge current I causes the voltage on capacitor 58 to fall at a constant rate indicated at 63 until the voltage level V is reached whereupon the output V F turns the current from generator 57 on and current 2I charges capacitor 58 along the straight line charging path 64. The slopes 63 and 64 are equal and opposite since the discharge rate I is cancelled and exactly equalled in the opposite direction by the charging current 21,. As soon as the excursion 64 reaches the voltage level E the flip-flop 59 changes state removing V as control voltage to interrupt the generation of 21 in current generator 57. The process repeats as indicated in FIG. 2B and with the input voltage V having a linear variation, the period of the control waveform V will be as indicated, a series of square waves having a period linearly increasing with time. This output V is applied on line 55 as the output of the voltage controlled period generator 54. Typically the shift period may vary for the 256 shift stages of storage delay herein disclosed between 4ps and 62.5us.

For expansion the waveforms in FIG. 2B would be modified in that the slope of Vc would be positive and start at the minimum value of Vp. These conditions in the circuit of FIG. 2A would generate an output pulse waveform V p with pulses of initial maximum width and pulse period linearly decreasing with time between the end points previously described. I

The output on line 55 is applied to a phase splitting driver circuit 65 which produces on outputs 66 and 67 phase opposed square waves corresponding to the square wave input on line 55 which are the 4),, (b drives for shifting analog signals through a pair of 256 storage stage analog shift registers 68 and 69.

The shift registers 68 and 69 are connected for processing disturbance cancellation introduced by the operation of the units at a varying shift pulse period. For this purpose the audio signal on line 22 from preamplifier 21 in FIG. 1 appears at input terminal 71 of an amplifier 72 which has its output connected as an input to analogshift register 68 and also connected to an inverter 73. The output of the inverter 73 is applied as the input signal for analog shift register 69. The outputs of the shift registers 68 and 69 are applied as the subtractive inputs to a differential unity gain amplifier at the input of an audio amplifier unit 74.

The just described circuit including the shift registers 68 and 69 and the amplifier 71 and inverter 72, to gether with the differential input amplifier 74 provides for frequency transformation of the input signal on line 71 and at the same time cancellation of the disturbances and distortion introduced by processing that signal through the shift registers 68 and 69.

The amplifier 74 further amplifies the difference signal obtained by combining the two inputs from the shift registers 68, 69 and supplies the amplified audio output signal on line 25. Also contained in the unit 74 is a zero crossing detector which provides on output line 75 a series of pulses representing the time of detection of zero crossings of the differenced input signal.

A blank-unblank control circuit 76 receives the zero crossing pulses on line 75 and operates when enabled by the blank enable signal on line 49 to produce an output blanking signal on line 77 which blanks the output of audio amplifier 74. This arrangement permits the output signal level on line to be blanked to zero signal level during the reset period for the shift registers and ramp generator controlled portions of the circuit. The circuit 76 is responsive to a signal on line 78 to terminute the blanking output on line 77 thereby permitting the signal on output line 25 to resume its signal level value.

A counter 81 produces an output on line 78 at the end of 256 counts corresponding to the lengthof the individual registers 68, 69 responsive to the pulses from line 55 applied on the counter input 82. When the counter 81 completes a count of 256 input pulses on line 82 it produces an output on line 78 that ends the blanking period pulse on line 77. A similar output to that on line 53 appearing on line 83 resets the counter 81. The interval timed by the counter 81 counting 256 counts of the pulse signal on line 55 provides blanking duration for the amplifier 74 sufficient to permit the pulses on line 55 after passing through drivers 65 to shift the registers 68, 69 and empty the contents thereof before unblanking occurs and audio output on line 25 is resumed. At the same time the shift pulses are applied to the registers 68, 69 to enter audio signal from terminal 71 through the amplifier and inverter 72, 73, so that the registers 68, 69 are full at the end of the blanking interval and ready to supply audio samples to the input of amplifier 74 and resume the next signal period.

In the event that no zero-crossing signal on line occurs during the enabled period established by the signal on line 49 prior to the occurrence of the reset signal on line 51, then the reset signal which is applied on line 83 to the counter 81 immediately causes a blank output signal on line 78 to the circuit 76 to blank the audio amplifier 74 by appropriate signal on line 77. Again, the action of the counter 81 removes the signal on line 78 to remove the blanking signal on line 77 at the end of the count of 256 pulses on input line 82. The audio output is thus blanked for the duration of the output pulse from reset one shot 52 plus the period required to count 256 counts in counter 81 plus the interval of time after the end of the 256 count for the detection of the next signal zerocrossing.

The blank-unblank control logic 76 comprises a D flip-flop and with the inputs indicated on lines 49, 75 and 78 the control of the output will be as indicated in FIG. 3. The enable input 49 permits blanking upon the occurrence of a zero crossing within the enable interval, and if it does not occur then the reset, one shot pulse on 83 forces the start of the blank interval by signal on line 78 which continues during the 256 counts in the counter 81. At the end of the 256 counts the signal on line 78 permits removal of the blanking signal at the occurrence of the next zero-crossing detection signal on line 75 causing it to switch the output on line 77.

For the purpose of resetting one shot 52 prior to the ramp end signal on line 51 and in synchronism with the detection of a zero crossing by blank control 76, the signal on line 77 is applied to pulse generator 101 to trigger reset one shot 52 upon the occurrence of a blank signal on line 77. The output of reset one shot 52 on line 53 thus resets the ramp generator 42 coincident with the detection of the first zero crossing after blank enable and the appearance of such signal on line 77. Thus, the gap in the audio output signal will ordinarily be reduced by a significant amount in all cases except when no zero crossing is detected during the full duration of the blank enable signal.

For time expansion, i.e., when C is less than one, the voltage signal on line 47 as applied to the blank enable unit 43 is compared with the E voltage on line 50, shown as 7.8 volts. to generate a ramp of opposite slope and substantially constant repetition interval in the ramp generator 42. Also a blank enable signal on line 49 as the ramp approaches its end value of 7.8 volts and the end reset pulse on line 51 are produced as herein described.

Referring now to FIG. 4A a detailed description of the construction of the ramp generator 42, blank enable unit 43 and reset one shot 52 and their interrelation will be given. In FIG. 4A the portion to the left of the dashed line generally relates to the ramp generator 42 shown in FIG. 2 and the portion in FIG. 4A to the right of the dashed line generally relates to the units 43 and 52 in FIG. 2. The ramp generator 42 comprises essentially a voltage capacitor 91 supplied by a constant current source 92 and a variable current source 93.

The current from the source 92 charges capacitor 91 and the current-through source 93 discharges capacitor 91. The current generator 93 is,voltage controlled by the voltage V on line 47 such that when the signal V is'equal to the value E the current discharge rate through source 93 is equal to the current charging rate from source 92 and no voltage change occurs across the capacitor 91. For other values of the voltage V the current drawn by source 93 will be either greater than or less than the current supplied by source 92 and a corresponding change in the voltage across the capacitor 91 will occur. .Thus the voltage across capacitor v9 1 will be either a positive ornegative slope ramp with the'sign of the slope determined by the relative magnitudes of V and E and the value of the slope determined by the difference in their magnitudes. This ramp voltage appears as an output on line 46 for supplying the input to voltage controlled period generator 54 as previously described.

For time compression the value of C will be greater than one and the voltage V will be greater than the voltage E and have a value determined by the selected value of compression ratio C and the voltage analog of that setting produced by motor control circuit 44 as modified by function circuit 45.

For controlling the ramp generation a series of volt age comparators 94, 95, 96, 97 and 98 are provided. The characteristic of the comparators 94-98 is to provide a ONE output if the plus input is greater than the minus input and a ZERO output for the opposite condition. Comparators 94, 95 and 96 have the ramp voltage across the capacitor 91 applied to the negative inputs thereof and this same voltage is applied to the positive input of comparator 98. The voltage E on line 50 is ap plied to the positive input of comparator 97 and to the negative input of comparator 98. The voltage V is applied to the negative input of comparator 97 and a voltagebctween V and the voltage E is applied to the positive input of comparator 96 by means of the voltage divider connecting lines 47 and 50 with the positive input to comparator 96 connected to the junction thereof. Comparator 94 has a +2 volt input to its positive terminal and comparator 95 has a +3 volt input to its positive terminal. The outputs of the comparators 9.4-98 are NAND connected to provide the blank enable signal on. line 49 and the reset pulse on line 51 as follows: Blank enable signal on line 49 is derived from NAND 105 which receives inputs from the output of comparator 96 and a NAND 106. The NAND 106 receives inputs from the output of comparator 95 and from an inverter 107 which has as its input the output of comparator 97.

. The, reset pulse on line 51 is derived from the output of a NAND 108 the inputs of which are derived from the outputs of NANDS 109 and 110. The inputs to NAND 109 are derived from the output of inverter 107 and the output of comparator 94. The inputs to NAND 110 come from the outputs of comparators 97 and 98.

. The .reset pulse on line 51 triggers reset one shot 52 to produce the reset pulse on line 53 which controls a gate 111 enabling it to pass signal from a buffer amplitier 112 when enabled. The output of the gate' 111 passes the output from amplifier 112 to establish the reset voltage level for capacitor 91 during reset. The voltage to which capacitor 91 will be reset is determined by the relative magnitude of V and E. When IV is greater than E the voltage input to amplifier 112 is derived from line 50 at the potential of E through resistor 1 13 and thus for compression ratios greater than one the reset is to a constant voltage level E. When V is less than E adiode 114 is poled to conduct and the input to amplifier 112 corresponds to the potential V and the capacitor 91 will be charged to the variable voltage level established by V on line 47.

. The operation of the circuit of FIG. 4A for time compression when C is greater than one will now be described with reference to FIG. 4B waveforms. The voltage V is greater than the voltage E thereby making comparator 97 have a zero output and disabling the NAND 110. Thus the output of 98 does not effect the production of reset signal on line 51. The output of inverter 107 is a one enabling NAND 109 thereby allowing comparator 94 to control the generation of reset pulse on line 51 when the voltage on capacitor 91 drops below the +2 volt level on the input of comparator 94. The output of inverter 107 at this time also has enabled the NAND 106 and thus the output of comparator 95 controls NAND to produce blank enable pulse on line 49 when the voltage on capacitor 91 drops below the +3 volt level. The output of NAND 96 is a one since voltage E is greater than the voltage at capacitor 91 for all values of V greater than E. Thus the charging rate for capacitor 91 is varied by the voltage V but the reset and blank enable signals are generated at a constant voltage level of two and three volts as shown in FIG. 48 with the resultant variation in repetition period for the ramp voltage as it falls from 7.8 volts to three and two volt levels at the various slopes determined by V For very small compression ratios greater than one the period would be very long and gradually reduce to approximately 30ms for C=2 and 20ms for C=3 as typical values. Since V establishes the ramp slope as approximately proportional to C l/C 1, the period for C l is approximately proportional to C l/C l. A typical value for the period would be 10 C l/C 1 milliseconds.

For C=l, V is equal to E and the charge and discharge currents for capacitor 91 will be equal. The voltage thereacross is constant thus effectively providing a zero slope ramp or fixed delay and no frequency conversion through the analog shift registers.

For the compression ratio C being less than one, V is less than E, and the output of comparator 97 is a one enabling NAND to permit the output of comparator 98 to control generation of the resetsignal on line 51. The output of inverter 107 is a zero thus disabling NANDS 106 and 109. For the condition of voltage across capacitor 91 becoming greater than E-R (E-V,, where the constant R might be approximately equal to 0.1 as determined by the voltage divider to which the positive input of comparator 96 is connected, the output of 96 becomes a zero and a blank enable output is produced on line 49 from NAND 105. When voltage 91 reaches the end of the ramp at E the output of comparator 98 becomes a one to produce a reset pulse on line 51 through NANDS 110 and 108. This action is shown in FIG. 4C where various levels of V are indicated as the starting point for the ramp voltage rise to the voltage E at 7.8 volts. The quantity ER (E--V varies somewhat with the value of V EC making the blank enable point on the ramp vary (shown exaggerated in FIG. 4C) but keeping the period of the ramp approximately constant. A typical repetition period for the system shown would be 40-50ms.

In certain speech compression applications, particularly in the case of expansion, it will be useful to reduce the disturbance caused by the gaps resulting from blanking between samples by filling such gaps with compatible signal. Referring now to FIG. 5, the general arrangement of the additional functional components required to fill such gaps with slightly delayed portions of the processed signal will be described. The signal from audio out line 25 of FIG. 2 is applied to a biasing network 172 for entry into an analog delay line 168. A constant frequency square wave 155 from generator 152 produces constant frequency complementary drive signals on lines 165 and 166, causing the signal in said delay line 168 to be delayed by a fixed amount at its output on line 151. The output 78 of counter 81 of FIG. 2 enables a D flip-flop 176 to produce an output gating signal on line 177 in which each change of state is triggered by a zero crossing pulse 175 from detector 174. Said gating signal 177 serves to unblank the delayed audio signal 151 between a beginning and ending zero crossing therefrom during the blank interval of the applied processed signal 25. The resultant gated-delayed signal, suitably normalized in amplifier 174 is then combined with the basic processed signal 25 in summing amplifier 148 to produce a composite audio signal on line 150.

FIG. 6 is a modification of FIG. 4A more suited to gap filling expansion. Clamped amplification circuitry 115, I16, 117 has been introduced to alter the characteristic of ramp reset during the expansion mode, (C l so as to allow variation of the period as a function of the compression ratio, C, as for the compression mode (C l while still maintaining a smooth transition in going from expansion (C l) to compression (C l) and vice-versa. For this purpose the voltage E on line 50 is connected as an input to amplifier 116 having gain of A-l/A the output of which is connected to the negative input of a differential amplifier 115. The positive input of amplifier 115 is the voltage V derived from line 47. The output of amplifier 115 is a voltage V' equal to A (V A-l /A E) which appears on line 118. y

The operation of the modification of FIG. 6 will now be described. Amplifiers 115 and 116 along with clamp I17 combine to functionally perform as an amplifier circuit whose output characteristic is as illusturated in FIG. 6A. This voltage is applied to the cathode of a diode 114 and to the negative input of comparator 97 on line 118.

In the compression mode (C l) when V' on line 118 is greater than E on line 50, comparator 97 will have a zero output and diode 114 will be non conducting as before, so that the operation will be the same in this mode as has been previously described with reference to FIG. 4A.

For the compression ratio C being less than one, V and thus V are each less than E, and the output of comparator 97 is a ONE enabling NAND 110 to permit the output of comparator 98 to control generation of the reset signal on line 51.

The reset pulse on-line 51 triggers reset one shot 52 to produce the reset pulse on line 53 which controls a gate 111 enabling it to pass signal from a buffer amplifier 112 when enabled. The output of the gate 111 65 passes the output from amplifier 112 to establish the reset voltage level for capacitor 91 during reset. When V is less than E and the output of unity gain amplifier a 112 corresponds to the potential V' of clamp amplifier 115, 116, 117 as characterized in FIG. 6A, diode 114 is poled to conduct so as to cause capacitor 91 to be charged correspondingly to voltage level V',;,- on

5 line 112. The modification in ramp period control is shown in FIG. 6B where various levels of V on line 118 are indicated as the starting point to the ramp voltage rise to the voltage E at 7.8 volts. Thus as V,;,- is decreased from a value equal to E, V' rapidly drops to 2 volts, corresponding to a V of about 7 volts and a compression ratio of about 0.92, and is then clamped at this 2 volt level. The effect of such a variation and clamping is to limit the sample period for C near unity such that the gap between samples for expansion at the ramp transition point corresponds to that for compression and this gap will be increased as V is decreased to the 2 volt level. Thereafter, for greater expansion ratios (smaller values of C) the gap will remain approximately constant while the sample period will be caused to vary accordingly. The gaps are so limited in order to avoid exceeding the limit of storage in line 168 and to conform to the characteristics of speech perception which would suggest longer samples for continuity, but with gaps short enough to avoid perceptible, repetitive or inconsistent filling.

Many modifications will now occur to those skilled in the art particularly in view of the broad features of applicants copending applications. In particular although the present disclosure is specific to one analog shift register as the delay line medium, various other forms of controlled delay elements used singly or in combination controlled alternately or otherwise are to be considered as within the scope of the invention as defined by the appended claims.

I claim:

1. A sound reproducer for playing a sound record at playback speed different than its recorded speed comprising means for transporting said sound record at a selected playback speed relative to a transducer to obtain an electric signal having frequency components altered by the ratio of said playback speed to said recorded speed;

means for frequency converting said electric signal with a repetitive varying time delay function having time delay variation adjusted in response to selection of said playback speed to be a function of C-l/C-H where C is said ratio of said playback speed to recorded speed;

means responsive to adjusting said delay variation for varying the repetitive interval of variation for said delay function approximately in direct relation to C+l/C1 for all values of C; and utilization means for the portions of said electric signal which have been frequency converted by said varying time delay function operable to produce a substantially continuous output signal.

2. Apparatus according to claim 1 in which said repetitive interval of variation is approximately l0 C+l/Cl milliseconds.

3. Apparatus according to claim 1 including:

blanking means operable for blanking said output sig nal between successive signal portions of said repetitive interval;

enabling means operative near the end of said repetitive interval for enabling said blanking means; zero crossing signal detector means for detecting zero crossings of said output signal; and

circuit means responsive to a detected zero crossing during the period of said enabling for operating said blanking means for a predetermined interval between said successive signal portions and resetting said delay variation to an initial value.

4. Apparatus according to claim 3 and including auxiliary fixed delay means for storing a predetermined interval of said output signal and means for combining the stored signal of said auxiliary delay means with said output signal to supply a composite audio output that includes said stored signal during said predetermined interval when said output signal is blanked.

5. Apparatus according to claim 4 and including means for selecting said ratio of playback speed to recorded speed to cover the range C l, C=l and C l.

6. In a speech compression-expansion system having variable delay line means repetitively varied to provide frequency transformation of signals passing through the line the combination comprising:

means for sensing zero crossing points on the signals derived from the output of said line;

enabling means for establishing an interval at the end of each repetitive variation;

blanking means responsive to detection of a zero crossing within said interval and if no such zero crossing is detected responsive to the end of said interval for blanking said signals derived from the output of said line until after the start of the next repetitive variation of said line;

fixed delay storage means coupled to the output of said variable delay line for supplying fixed further delay for signals which have been frequency transformed by said variable delay line; and

means for combining the outputs of said variable delay line and said fixed delay storage means in accordance with operation of said blanking means to form a composite output signal having the blanking interval for said signals filled with signals having said fixed further delay.

UNITED STATES PATENT AND TRADEMARK OFFICE CERTIFICATE OF CORRECTION PATENT NO. 2 3,869,708 DATED I March 4,

INVENTOR(S) Murray M. Schiffman It is certified that error appears in the above-identified patent and that said Letters Patent are hereby corrected as shown below:

In the legend: [73] Assignees: correct the name of Murray M. Shiffman" to Murray M. Schlffman Signed and Scaled this second D21) Of September 1975 [SEAL] A ttesr:

RUTH C. MASON C. MARSHALL DANN Alresti'ng ()jficer (mnmissioner nfPalents and Trademarks 

1. A sound reproducer for playing a sound record at playback speed different than its recorded speed comprising means for transporting said sound record at a selected playback speed relative to a transducer to obtain an electric signal having frequency components altered by the ratio of said playback speed to said recorded speed; means for frequency converting said electric signal with a repetitive varying time delay function having time delay variation adjusted in response to selection of said playback speed to be a function of C-1/C+1 where C is said ratio of said playback speed to recorded speed; means responsive to adjusting said delay variation for varying the repetitive interval of variation for said delay function approximately in direct relation to C+1/C-1 for all values of C; and utilization means for the portions of said electric signal which have been frequency converted by said varying time delay function operable to produce a substantially continuous output signal.
 2. Apparatus according to claim 1 in which said repetitive interval of variation is approximately 10 C+1/C-1 milliseconds.
 3. Apparatus according to claim 1 including: blanking means operable for blanking said output signal between successive signal portions of said repetitive interval; enabling means operative near the end of said repetitive interval for enabling said blanking means; zero crossing signal detector means for detecting zero crossings of said output signal; and circuit means responsive to a detected zero crossing during the period of said enabling for operating said blanking means for a predetermined interval between said successive signal portions and resetting said delay variation to an initial value.
 4. Apparatus according to claim 3 and including auxiliary fixed delay means for storing a predetermined interval of said output signal and means for combining the stored signal of said auxiliary delay means with said output signal to supply a composite audio output that includes said stored signal during said predetermined interval when said output signal is blanked.
 5. Apparatus according to claim 4 and including means for selecting said ratio of playback speed to recorded speed to cover the range C<1, C 1 and C>1.
 6. In a speech compression-expansion system having variable delay line means repetitively varied to provide frequency transformation of signals passing through the line the combination comprising: means for sensing zero crossing points on the signals derived from the output of said line; enabling means for establishing an interval at the end of each repetitive variation; blanking means responsive to detection of a zero crossing within said interval and if no such zero crossing is detected responsive to the end of said interval for blanking said signals derived from the output of said line until after the start of the next repetitive variation of said line; fixed delay storage means coupled to the output of said variable delay line for supplying fixed further delay for signals which have been frequency transformed by said variable delay line; and means for combining the outputs of said variable delay line and said fixed delay storage means in accordance with operation of said blanking means to form a composite output signal having the blanking interval for said signals filled with signals having said fixed further delay. 